%Q Control Bits
The following %Q Control Bits are transferred automatically from the CPU to the IOP
each sweep. The actual addresses of the Control Bits depend on the starting address
configured for the %Q references (see Section 3 for these configuration details).
numbers listed in the following table are offsets from this %Q reference address.
Enable Output 1
Enable Output 2
Enable Output 3
Enable Output 4
Enable Output 5 (only if cfg = enabled)
Reset Strobe 1 (Input 9 latch)
Enable Output 6 (only if cfg = enabled)
Reset Strobe 2 (Input 10 latch)
Enable Output 7 (only if cfg = enabled)
Reset Strobe 3 (Input 11 latch)
Enable Output 8 (only if cfg = enabled)
Reset Strobe 4 (Input 12 latch)
Reset Preload Latch
* Bit numbers are offsets from the starting address for %Q References.
Applies to AQUADB function only.
%Q Control Bit Descriptions
Enables each hardware Output (ON = Enable). If the configuration for Outputs 5–8 are
DISABLED, then these corresponding output bit commands have no effect.
This command clears the respective strobe latch condition so the next strobe can be
captured and reported via the corresponding %I bits. If this %Q bit is held ON, the %I
status bit will stay OFF and every strobe input pulse will cause new strobe data to be
captured in the associated %AI strobe register.
This initiates the Home command sequence. When the Home Marker Input is
recognized, the input counter will be preloaded with the configured home value, and
the Home Found %I indication will be set.
This command clears the Preload Latch status after it has been set by the Preload switch
Input. If this command is left on, it will allow all Preload switch inputs to be effective.
This command preloads the input counter with the configured preload value. The
Preload Latch status %I indication will not be set by this command since it only applies
to the Preload faceplate input.
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